Computer Architecture and Assembly Languages

Sketch of Lecture Sessions

1. Class introduction (week 1)
   1. Goals and expectations of this course
   2. Block diagram of a generic computer and basic program execution
   3. Basic data representation: bits, bytes, words
   4. Refinement of the block diagram: address and data busses, address space
2. Basic CPU organization (week 1)
   1. CPU block diagram
   2. Registers, accumulators, flags
   3. ALU, FPU, and special functions
   4. Control and data paths, bus interface
   5. Instruction sequencing and execution speed issues
3. Assembly Language and Machine Code in General (Week 2-4)
   1. Data formats
      • Unsigned binary numbers
      • Binary Coded Decimal (BCD), EBCDIC
      • ASCII characters and strings
      • Signed numbers (two's complement and others)
   2. Opcodes and instruction format
      • Main opcode and modifier fields
      • Fixed and variable length instructions
      • Mnemonics for opcodes and the idea of assembly language
   3. Operands and addressing modes
      • Number and size of operands
      • Assembly language syntax basics
      • Register addressing
      • Immediate addressing
      • Direct addressing
      • Register indirect addressing
      • Offsets and relative addressing
      • Segments and the resulting addressing modes
      • Indexed addressing
      • Indirect addressing
      • Auto-increment, auto-decrement, and stacks
      • Other addressing modes: current page, 0-page, indirection bits.
   4. Machine instruction categories
   5. Data transfer operations
      • MOVE instructions
      • Exchange
      • Repeated move instructions (strings)
      • Special move instructions
   6. Arithmetic and logical operations
      • Bitwise AND, OR, NOT, XOR
      • Shift (logical and arithmetic), rotate
      • Compare
      • Negate
      • Add and subtract (and extending the operands)
   7. Bit manipulation instructions
      • Flag manipulation
      • Bit and bit field manipulation
   8. Program flow control operations (branch, subroutine call)
      • Branching addressing modes
      • jump instructions
      • Branch and conditional JUMP instructions
      • Call and return instructions
      • Looping instructions
   9. Input-output operations
      • IN instructions
      • OUT instructions
      • Memory mapped input output systems
      • I/O mapped input output systems
   10. Machine control operations and interrupts
       • Protection support instructions
       • Interrupts: hardware and software
       • Atomic operations
       • Special control operations
   11. Pseudo-operations and the process of assembly and linking
       • Defining space for variables
       • Defining constant data
       • Initial addresses for code and data
       • Defining constants
4. Assembly language programming issues (weeks 5-6)
   1. High-level language support
      • Parameters, local variables
      • High-level language calling convensions
      • Architecture support for high-level languages
   2. Co-routines and "processes"
      • Using several stacks
      • State of computation ("process")
      • Re-entrant code
      • Transfer of control: RESUME operation
   3. Pseudo-operations and the process of assembly and linking
      • Macros (outline)
      • Assembly: pass I
      • Assembly: pass II
      • Address fixup tables, relocatable object files
      • The linking process and executable files
      • Libraries, dynamic linking
   4. Monitors and debuggers: debugging assembly language programs
      • Viewing and modifying registers and data
      • Running, single-stepping, breakpoints
      • Trace and watch
      • Symbolic debuggers
5. A RISC Architecture and Assembly Language - MIPS (weeks 7-8)
   1. RISC vs. CISC
   • Computer performance measures
   • CISC design basics
   • RISC design basics
   2. MIPS organization and architecture
   • Register set
   • Instruction formats
   • Addressing modes
   3. MIPS assembly language
   • Branch instructions
   • Arithmetical and logical instructions
   • Load/store instructions
   4. The arithmetical and logical unit (ALU)
   • Arithmetic operations on integers
   • Logical operations
   • Status bit generation
   • MIPS ALU
   5. The control unit and the datapath
   • The Branch execution unit
   • Hard wired control
   • Single cycle control
   • The MIPS Data-path
   6. Processor bus interface
   7. Microprogramming
   • The control logic unit
   • Multiple cycle hard-wired control
   • Microprogram control
6. Issues in modern architectures (weeks 9-12)
1. Advanced data formats: floating point standards
• Addition, subtraction and multiplication on fixed point numbers
• The IEEE standard for floating point number representation,
•  Addition subtraction and multiplication of floating point numbers
• The MIPS floating Point Unit
2. Associative memory and caches
• Locality of reference
• The "small is fast" principle
• Stack memory
• Modular memory
• Associative memory
3. Address mapping (paging, segmentation, virtual memory)
• Direct mapping
• Associative mapping
• Set-associative mapping
• Cache write policies
• Cache design principles
• Cache management in the MIPS
• Hardware support of virtual memory
• Memory management in the MIPS
4. Pipelining
• Principles of pipeline design
• Instruction pipeline
• Functional pipeline
• Synchronization and control of pipelines
• The MIPS instruction pipeline
• Performance of pipelined computers
5. Co-processor and multiprocessor systems
• Classification of parallel computers
• Speedup of parallel systems
• Special purpose co-processors
• Array processors and vector processor
• The ILLIAC IV
• Systolic arrays
• Multiprocessor systems
• Data decomposition vs functional decomposition
7. Inter-process/processor communication (week 13)
1. Error detection and correction
   • Parity and error detection
   • Principles of error correction
   • Single-bit error correction: Hamming code
   • Hamming + parity and beyond
   • Correcting erasures
2. Parallel communication (hardware handshake)
3. Serial communication
   • USART device, serial communication
   • Hardware level: RS232, RS422
   • Hardware and software (XON-XOFF) handshakes

Online Exercises

Web pages for exercise sessions and assignments can be accessed here.

Other Online Material

1. Slides for week 1 lectures, (sans figures - postscript).
2. Slides for week 8 lectures, (postscript).
3. Slides from Patterson and Hennesy. Copyright 1998 Morgan Kaufmann Publishers.
   1. Chapters 1-4, powerpoint, or postscript.
   2. Chapter 5, powerpoint, or postscript.
   3. Chapter 6, powerpoint, or postscript.
   4. Chapters 7-9, powerpoint, or postscript.

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