Computer Architecture (and Low-Level Programming)

Sketch of Lecture Sessions

1. Class introduction (week 1)
   1. Goals and expectations of this course
   2. Review of basic architecture: block diagram of a generic computer and basic program execution
   3. Architecture design goals
2. Basic low-level programming issues (weeks 2-6)
   1. Opcodes and instruction format
      • Main opcode and modifier fields
      • Fixed and variable length instructions
      • Mnemonics for opcodes and the idea of assembly language
   2. Operands and addressing modes
      • Number and size of operands
      • Assembly language syntax basics
      • Register addressing
      • Immediate addressing
      • Direct addressing
      • Register indirect addressing
      • Offsets and relative addressing
      • Segments and the resulting addressing modes
      • Indexed addressing
      • Indirect addressing
      • Auto-increment, auto-decrement, and stacks
      • Other addressing modes: current page, 0-page, indirection bits.
   3. Machine instruction categories
      1. Data transfer operations
         • MOVE instructions
         • Exchange
         • Repeated move instructions (strings)
         • Special move instructions
      2. Arithmetic and logical operations
         • Bitwise AND, OR, NOT, XOR
         • Shift (logical and arithmetic), rotate
         • Compare
         • Negate
         • Add and subtract (and extending the operands)
      3. Bit manipulation instructions
         • Flag manipulation
         • Bit and bit field manipulation
      4. Program flow control operations (branch, subroutine call)
         • Branching addressing modes
         • jump instructions
         • Branch and conditional JUMP instructions
         • Call and return instructions
         • Looping instructions
      5. Input-output operations
         • IN instructions
         • OUT instructions
         • Memory mapped input output systems
         • I/O mapped input output systems
      6. Machine control operations and interrupts
         • Protection support instructions
         • Interrupts: hardware and software
         • Atomic operations
         • Special control operations
      7. Pseudo-operations and the process of assembly and linking
         • Defining space for variables
         • Defining constant data
         • Initial addresses for code and data
         • Defining constants
   4. High-level language support
      • Parameters, local variables
      • High-level language calling convensions
      • Architecture support for high-level languages
   5. Pseudo-operations and the process of assembly and linking
      • Macros (outline)
      • Assembly: pass I
      • Assembly: pass II
      • Address fixup tables, relocatable object files
      • The linking process and executable files
      • Libraries, dynamic linking
   6. Machine control operations and interrupts
      • Protection support instructions
      • Interrupts: hardware and software
      • Atomic operations
      • Special control operations
   7. Monitors and debuggers: debugging low-level programs
      • Viewing and modifying registers and data
      • Running, single-stepping, breakpoints
      • Trace and watch
      • Symbolic debuggers
3. Advanced low-level programmaing issues (weeks 7-9)
   1. Co-routines and "processes"
      • Using several stacks
      • State of computation ("process")
      • Re-entrant code
      • Transfer of control: RESUME operation
   2. Position-independent code
   3. Self-modifying code
   4. Executable file computer viruses
4. Issues in modern architectures (weeks 10-12)
1. Computer performance measures
2. RISC vs. CISC
3. Address mapping
• Paging
• Segmentation
• Hardware support of virtual memory
4. Pipelining
• Principles of pipeline design
• Instruction pipeline
• Functional pipeline
• Synchronization and control of pipelines
• Performance of pipelined computers
5. Co-processor and multiprocessor systems
• Classification of parallel computers
• Speedup of parallel systems
• Special purpose co-processors
• Array processors and vector processor
• The ILLIAC IV
• Systolic arrays
• Multiprocessor systems
5. Communication (week 13)
1. Error detection and correction
   • Parity and error detection
   • Principles of error correction
   • Single-bit error correction: Hamming code
   • Hamming + parity and beyond
   • Correcting erasures
2. Parallel communication (hardware handshake)
3. Serial communication
   • USART device, serial communication
   • Hardware level: RS232, RS422
   • Hardware and software (XON-XOFF) handshakes

Online Exercises

Web pages for exercise sessions and assignments can be accessed here.

Other Online Material

1. Slides for week 1 lectures, (sans figures - postscript, pdf),ppt .
2. Slides for week 2-3 lectures, (Instruction formats and addressing modes postscript, pdf), (Instruction categories postscript, pdf).
3. Slides for week 4-5 lectures, (postscript, pdf).
4. Example co-routine code main.c and co.s.
5. Example assembly code with macros, and resulting listing file.
6. Files used in class on position-independent code.
7. Slides for class on codes and communication, pdf).
8. For advanced architecture features (last 3 weeks of course).
   • Slides from Patterson and Hennesy. Copyright 1998 Morgan Kaufmann Publishers. Chapters 1-4, Chapter 6 (pipelining). Material in course is chapters 1-2, and basics in chapter 6.
   • Simplified generic presentation by D. Abramson, lecture notes. This course uses parts of chapter 4, chapter 5, and chapter 8.

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